This invention relates generally to logic circuits and more particularly, it relates to complementary metal-oxide semiconductor (CMOS) circuit design of storage devices such as flip-flops, data shift registers, memory elements and the like. Most especially, it relates to a CMOS D-type flip-flop circuit stage having a single N-channel field-effect transistor (FET) for data transfer in a master section and in a slave section. This permits the use of a two-phase non-overlapping clock generator for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.
A CMOS D-type dynamic flip-flop circuit of the prior art is shown in FIG. 1 which requires both a N-channel MOS transistor T1 and a P-channel MOS transistor T2 in the master section and in the slave section. Due to this, a non-overlapping clock generator could not be used since the flip-flop circuit would be susceptible to the problem of feedthrough or racethrough. In another words, both of the P-channel transistors T2 would be partially turned on simultaneously whereby the data input would feed through to the successive stages. Thus, this prior art flip-flop circuit required the use of a specially-designed clock to insure proper transition time relative to the inverter delay. Further, this prior art circuit necessitated the routing of two lines to successive stages. In order to eliminate the routing of two lines, a flip-flop circuit of the prior art was constructed as shown in FIG. 2. However, the circuit of FIG. 2 required the use of an additional inverter gate I1 which increased its cost for manufacturing.
A CMOS D-type static flip-flop circuit of the prior art is shown in FIG. 3. This circuit is similar to the dynamic flip-flop circuit of FIG. 1 and requires the addition of a regeneration circuit formed of a N-channel MOS transistor T3, a P-channel MOS transistor T4 and an inverter gate I2 in both the master section and the slave section. The circuit of FIG. 3 suffered from the same disadvantages of FIG. 1 in that racethrough would occur if a non-overlapping clock generator was used. In order to solve the problem of racethrough, a flip-flop circuit of the prior art was constructed as shown in FIG. 4. However, the circuit of FIG. 4 required the generating and routing of four lines. Furthermore, there was needed to generate separate clock pulses providing true and false clock phases to the master section which differed from true and false clock phases supplied to the slave section. The problem of racethrough was overcome by delaying the clock pulses to the slave section relative to the clock pulses applied to the master section. A clock generator which accomplished this result is illustrated in FIG. 5.
It would therefore be desirable to provide CMOS D-type flip-flop circuits which are immune to the possibility of racethrough but is capable of utilizing a standard or conventional non-overlapping clock generator.